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| Annex 1 | |||
| 5.2.2.2 Verification during Development (Design Verification) |
Verification during Development (Designverifikation)
 Contents
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1 Identification/Definition of the Method
/Brix, 1986/
Verification during Development may be seen as a special case of the Classical Design Verification. Every design step (what is already a refinement of a specification) is proven immediately.
2 Brief Characteristic of the Method
Prior to the next design step every design step is proved. The method is identical to the Classical Design Verification if the refinement of a specification consists of only one design step. After the last design step the required formal specification is available.
3 Application of the Method in the V-Model
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4 Interfaces
There is an interface to FS - Formal Specification. The Verification during Development has to be suited to the formal specification language.
5 Further Information
- not applicable -
6 Literature
| /Brix, 1986/ | By means of the examples CARTESIANA, a verification tool of Siemens, the basic features of "Program Verification during Development" are explained |
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| /Brock, 1990/ | Handbook for the formal specification language RAISE, a further development of the formal specification language VDM extended by the possibility of algebraic specification and b parallelism |
| /Jones, 1990/ | Describes VDM and its basis |
| /Kersten, 1990/ | Several reports on "formal specification and verification" |
| /Nicholls, 1990/ | Articles on the Z User workshop 1989, mainly concerning Z |
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